1. Field of the Invention
The present invention relates to a nonvolatile memory device, and more particularly to a nonvolatile memory device including a data latch circuit which latches program information to output the latched information.
2. Description of the Background Art
In recent years, attention has been paid to an FPGA (Field Programmable Gate Array) as a rewritable large-scale integrated circuit.
An FPGA is a semiconductor device capable of changing its functions later on, so as to perform predetermined operations by providing external data and the like to an internal circuit.
The FPGA is used as a prototype for devices because of its feature in that the time of development is shorter than that of a gate array, and has been used these years as a prototype device for a cellular phone or an ETC (Electronic Toll Collection system).
A FPGA is generally provided with: a plurality of logical blocks; a plurality of switch circuits for switching the connection relationship (signal paths) of the plurality of logical blocks; and a control circuit for controlling the plurality of switch circuits. The control circuit latches program information programmed in a predetermined region to selectively supply the latched information to the switch circuit in order to control the switch circuits. This results in the switching of the connection relationship (signal paths) between the plurality of logical blocks to change the functions of the FPGA.
Various kinds of latch circuits have been proposed as a circuit for latching program information. Conventionally, there has been used a configuration of storing program information into a so-called SRAM (Static Randam Access Memory) element while performing switching control by using a data latch circuit for latching the stored data.
However, in the data latch circuits employing an SRAM element which is a volatile element, latched program information is lost after the power supply is suspended. This makes it necessary to temporarily download the program information to be latched in the data latch circuit, every time power is turned on, which might interfere with high-speed operations.
Japanese National Patent Publication No. 2002-511631 proposes a data latch circuit capable of latching storage data to output the latched storage data by using a nonvolatile element, without downloading the program data when power is turned on.
However, an FPGA is required to change various functions by performing various patterns of switching control, and the changing of functions requires rewriting program information that has been temporarily stored in the data latch circuit.
It is therefore difficult to efficiently change the functions of an FPGA at high speed.